1. Field of the Invention
The invention relates to nonvolatile memory, and particularly a method for programming and erasing, a nonvolatile memory array and a non-volatile memory array structure.
2. Description of the Related Art
Non-volatile memory devices of the type commonly referred to in the art as EPROM, EEPROM, or Flash EEPROM serve a variety of purposes, and are hence provided in a variety of architectures and circuit structures.
Some of the main objectives of non-volatile memory device designers are to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one such device that must meet these challenges. In some applications, such as flash memory cards, density is at a premium, while in applications such as programmable logic devices (PLD""s), reliability is more important and space is at less of a premium.
The conventional xe2x80x9cstacked gatexe2x80x9d EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In addition, designers strive to reduce power requirements of devices by reducing program and erase voltage requirements.
An alternative to Fowler-Nordheim tunneling-based cell structure is presented in Ranaweera, et al., xe2x80x9cPerformance Limitations of a Flash EEPROM Cell, Programmed With Zener Induced Hot Electrons,xe2x80x9d University of Toronto Department of Electrical Engineering (1997). Discussed therein is a flash EEPROM cell which accomplishes programming and erase by establishing a reverse breakdown condition at the drain/substrate junction, generating hot electrons which are then injected into the floating gate to program the cell.
U. S. Pat. No. 6,064,595, inventors Stewart G. Logie, Sunil D. Mehta and Steven J. Fong, issued May 16, 2000; co-pending U.S. patent application Ser. No: 09/217,648, inventors Christopher O. Schmidt and Sunil D. Mehta, filed Dec. 21, 1998; Ser. No. 09/277,441, inventors Xiao-Yu Li, Steven J. Fong and Sunil D. Mehta, filed Mar. 26, 1999; Ser. No. 09/217,646, inventor Sunil D. Mehta, filed Dec. 21, 1998; Ser. No. 09/221,360, inventor Stewart G. Logie, filed Dec. 28, 1998; Ser. No. 09/220,469, inventor Christopher O. Schmidt, filed Dec. 23, 1998; all assigned to the assignee of the present application, describe various non-volatile memory structures wherein a junction breakdown between an n type region and a p type region in a substrate or in a polysilicon structure overlying a substrate is used to generate hot electrons which are then drawn onto a floating gate structure based on the potential applied to the floating gate via a program junction or region. Each of the aforementioned applications is hereby specifically incorporated by reference. The cells described therein have a number of advantages over conventional xe2x80x9cstacked gatexe2x80x9d type memory cells.
Each non-volatile element includes a floating gate which stores trapped electrons or holes to indicate the programmed or erased state of the element, a program junction region, used to control migration of holes or electrons onto the gate, and control elements, such as a sense element (which may comprise a transistor) and read element. In co-pending application Ser. No. 09/217,648, a non-volatile cell structure is described wherein the programming element is separated from the read path elements, allowing thinner oxides and lower operating voltages to be used in the element.
Generally, arrays of individual memory cells are formed on a single substrate and combined with sense and read circuitry, and connected by row-wise and column-wise conductive regions or metallic conductors to allow for array wide bulk program and erase as well as selected bit programming.
Normally, such arrays are arranged in rows and columns so that control voltages may be applied to the program, sense and read elements in a selective manner.
In conjunction with the use of the junction breakdown memory element, U.S. Pat. No. 6,064,595 describes an array programming scheme using a p-well, row wise biased elements with N+ active regions are controlled using divisions of the program voltage Vpp in a novel manner.
FIGS. 1 and 2 show an array configuration and exemplary cell cross section disclosed in U.S. Pat. No. 6,064,595.
A two-by-two matrix 100 of the program and sense elements of non-volatile memory cells 120,130,140,150 is shown. While only the sense transistor, such as transistor 123, is shown for each cell, typically the sense element is coupled to read path circuitry, such as a read element. Further, while only four cells are shown, it will be understood that these four cells generally comprise a portion of a larger array of cells. Cell 120 is exemplary of each cell in the matrix. Cell 120 includes capacitor 122, the floating gate sense transistor 123, and an avalanche/Zener injector diode or program element 124. Element 124 includes a drain region 124-2 connected to a first program line (WBL)n and a source region 124-4, and floating gate (FG) at region 124-6. Nonvolatile floating gate transistor 123 includes a source 123-2 and drain 123-6, and floating gate (FG) connected at point 123-4. Floating gate (FG1) is connected to the control gate (ACG) by the control gate capacitor 122. Transistor 123 provides the sense element for circuitry (such as read circuitry, not shown) which is utilized in detecting the state of the cell. The source and drain of transistor 123 may be connected to read circuitry and electrical couplings as discussed above, or in any number of other well-known manners.
Cells 120 and 130 share a first common array control gate (ACG) connection ACGn at terminals 121, 131, coupled to capacitors 122, 132, respectively. Likewise, each element 124, 134, shares a first common Word Line Connector WWLn.
A particular single-poly cross-section configuration of the memory array along the WBLn line (the program element) is shown in FIG. 2. FIG. 2 shows a cross-section of the polysilicon structure of floating gate (FG), and diffused or implanted conductive lines WBLn, and WWLn in relation to a memory cell, such as cell 120.
Each word write line is formed, as shown in FIG. 2, by using a common P-well region for each row, which is biased by P+ word write line WWLn, allowing the substrates of each cell in a row 124, 134 to be commonly biased. Likewise, cells 140 and 150 share a P-well 161, and second common word line WWLm, and are connected to a second common control gate connection ACGm. Cells 120 and 140 share a first common program line WBLn, and cells 130 and 150 share a second common program line WBLm. In each cell, a portion of floating gate FG is coupled to element 124. Each program element (for example 120) includes a p+ implant region 128 connected to the particular word write line (WWL), and implanted n+ regions 124-2, 124-4 adjacent to implanted p+ regions 125-1, 125-2 underlying floating gate FG. It is the junction breakdown between the p+ regions, biased by the p-well and WWL voltage, and the n+ regions, in this case region 124-2 coupled to the write bit line (WBL) which provides hot electrons or holes for programming of the floating gate (FG). In this description, only one p/n junction is used for programming. It should be recognized that the junction between regions 125-1 and 124-4 could also be utilized in conjunction with the junction between regions 125-2 and 124-2 to program and erase over different regions of the gate oxide 126.
Table 1 shows one exemplary application of the voltages applied on the respective conductors in accordance with the present invention:
So applied, only one cell in the array, in this case cell 120, will have an avalanche injector element which is in breakdown mode, while each of the other cells will not be in breakdown mode assuming a breakdown state of 6V, where six volts are above the avalanche breakdown mode, while three volts are below. Hence, in one embodiment, elements 124, 134, 144, 154 are only in avalanche breakdown mode when WBL equals approximately six volts and WWL equals approximately zero volts for an individual cell. The selected cell (120 in this example) may be charged to +Ve or xe2x88x92Vp (and hence erased or programmed) according to the bias on the ACG. Cells 130 and 140 have a voltage across their P/N junctions of only 3 volts and hence are not in avalanche or Zener breakdown mode. Cell 150 has three volts on both WWLm and WBLm and hence there is zero voltage across the breakdown region.
In the above described embodiment, row-wise pxe2x88x92type wells are utilized. It would be advantageous to provide an nxe2x88x92type well structure cell, which would be individually selectable for use in a pxe2x88x92type substrate, more commonly found in commercial applications. Also, the p-well usually is deeper than the isolation and consequently the p-well to p-well spacing is quite large, making the cell size large as well. Moreover, if isolated cells are derived in a pxe2x88x92type substrate as desired, a double-well embodiment is required, necessitating additional well to well spacing due to p-well migration.
Each of the aforementioned configurations presents advantages and disadvantages in use in particular applications. Nevertheless, improvements in both the structure of individual cells and the manner in which they are connected together will result in more reliable, stable, faster, smaller and lower power devices which can be programmed and erased at lower voltages.
In one aspect, the invention, roughly described, comprises a program element for a memory cell formed in a substrate. The element includes a well region of an opposite conductivity type as said substrate formed in the substrate; a first active region formed in the well and having the same conductivity type as said well; and a second active region formed in the well and having a conductivity type opposite to that of the first conductivity type, and having a junction with said first active region.
In one embodiment, the first active region is an n+ region and the second active region is a p+ region formed in an n-well. In another aspect, the second active region comprises a lightly doped region and said cell further includes a third region of said second conductivity type positioned adjacent to the second active region.
In a further aspect, the invention comprises an array of memory cells each of which includes a well formed in a semiconductor substrate; a first impurity region formed in the well; a second region of opposing conductivity type formed adjacent to the first region; and at least a portion of a floating gate formed over the pxe2x88x92 region.
In a still further aspect, the invention is a memory cell for a non-volatile device. The cell includes a reverse breakdown program element formed in an n-well in the semiconductor substrate. The program element includes a first active region formed in the well and having the same conductivity type as said well; and a second active region formed in the well and having a conductivity type opposite to that of the first conductivity type, and having a junction with said first active region; and a floating gate overlying the reverse breakdown element. The memory cell may further include a sense element coupled to the floating gate and a read element coupled to the sense element.
In yet another aspect, the invention is a method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array. The method includes the steps of: applying a first voltage on a first column node connecting a first column of said cells to bias a first set of wells associated with a first set of cells, and a second voltage on a second node connecting a second column of said cells to bias a second set of wells associated with a second set of cells; and applying a third voltage on a first row node connecting a first row of said cells intersecting said first and second sets of cells, and applying said second voltage on a second row node connecting a second row of said cells intersecting said first and second sets; wherein the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row.